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FPGA CNN Accelerator

An end-to-end Verilog accelerator for MNIST inference.

  • TypeEngineering
  • PeriodSep 2024 — Jan 2025
  • AffiliationCourse Engineering Project
  • StatusCompleted

Overview

Designed an end-to-end convolutional neural network accelerator for MNIST handwritten-digit recognition on FPGA.

  • Implemented the hardware with Verilog.
  • Used separate RAM and buffer structures in the architecture.
  • Designed a pipelined computation flow.
FPGAVerilogCNN

This public overview does not include private code, unpublished measurements, or confidential details from industry collaborations.